Messages in this thread | | | Date | Mon, 26 Jun 2023 11:36:52 +0200 | From | Sascha Hauer <> | Subject | Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz |
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On Wed, Jun 14, 2023 at 04:47:50PM +0300, Alibek Omarov wrote: > PLL rate on RK356x is calculated through the simple formula: > ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2) > > The PLL rate setting for 78.75MHz seems to be copied from 96MHz > so this patch fixes it and configures it properly. > > Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com> > Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
> --- > drivers/clk/rockchip/clk-rk3568.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c > index 5dae960af4ce..48b8d06c305c 100644 > --- a/drivers/clk/rockchip/clk-rk3568.c > +++ b/drivers/clk/rockchip/clk-rk3568.c > @@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { > RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), > RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), > RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), > - RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), > + RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
refdiv = 4 fbdiv = 315 postdiv1 = 6 postdiv2 = 4
((24000000 / 4) * 315) / 6 / 4 = 78750000
LGTM
Sascha
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