Messages in this thread Patch in this message | | | From | Clément Léger <> | Subject | [RFC PATCH 3/6] riscv: allow S-mode to handle misaligned traps | Date | Sat, 24 Jun 2023 14:20:46 +0200 |
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Now that we will be able to configure the SBI to let us handle the traps, let this misalignment handling be available for S-mode.
Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/kernel/traps.c | 7 ------- 1 file changed, 7 deletions(-)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c258b78c925..b544cdd52dd2 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -149,12 +149,6 @@ DO_ERROR_INFO(do_trap_insn_illegal, SIGILL, ILL_ILLOPC, "illegal instruction"); DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); -#ifndef CONFIG_RISCV_M_MODE -DO_ERROR_INFO(do_trap_load_misaligned, - SIGBUS, BUS_ADRALN, "Oops - load address misaligned"); -DO_ERROR_INFO(do_trap_store_misaligned, - SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned"); -#else int handle_misaligned_load(struct pt_regs *regs); int handle_misaligned_store(struct pt_regs *regs); @@ -199,7 +193,6 @@ asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs irqentry_nmi_exit(regs, state); } } -#endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_s, -- 2.40.1
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