Messages in this thread | | | Date | Fri, 23 Jun 2023 16:11:59 +0530 | Subject | Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3 | From | Sricharan Ramabadhran <> |
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On 6/23/2023 3:52 PM, Konrad Dybcio wrote: > On 23.06.2023 11:44, Sricharan Ramabadhran wrote: >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 >> pcie slave addr size was initially set to 0x358, but >> was wrongly changed to 0x168 as a part of >> 'PCI: qcom: Sort and group registers and bitfield definitions' > Surely not, this commit only moved the definition containing 0x358 up. >
Oops, infact it was the one just below, this one which changed it.
"PCI: qcom: Remove PCIE20_ prefix from register definitions"
Will fix this in V2.
Regards, Sricharan
> Konrad >> Fixing it back to right value here. >> >> Without this pcie bring up on IPQ8074 is broken now. >> >> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 4ab30892f6ef..59823beed13f 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -43,7 +43,7 @@ >> #define PARF_PHY_REFCLK 0x4c >> #define PARF_CONFIG_BITS 0x50 >> #define PARF_DBI_BASE_ADDR 0x168 >> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ >> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ >> #define PARF_MHI_CLOCK_RESET_CTRL 0x174 >> #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 >> #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
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