Messages in this thread | | | Date | Fri, 23 Jun 2023 19:56:58 -0300 | From | Jason Gunthorpe <> | Subject | Re: [RFC PATCH 00/21] iommu/amd: Introduce support for HW accelerated vIOMMU w/ nested page table |
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On Fri, Jun 23, 2023 at 03:05:06PM -0700, Suthikulpanit, Suravee wrote:
> For example, an AMD IOMMU hardware is normally listed as a PCI device (e.g. > PCI ID 00:00.2). To setup IOMMU PAS for this IOMMU instance, the IOMMU > driver allocate an IOMMU v1 page table for this device, which contains PAS > mapping.
So it is just system dram?
> The IOMMU hardware use the PAS for storing Guest IOMMU information such as > Guest MMIOs, DevID Mapping Table, DomID Mapping Table, and Guest > Command/Event/PPR logs.
Why does it have to be in kernel memory?
Why not store the whole thing in user mapped memory and have the VMM manipulate it directly?
Jason
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