| Date | Thu, 1 Jun 2023 14:42:17 +0100 | From | Jonathan Cameron <> | Subject | Re: [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address |
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On Tue, 23 May 2023 18:22:10 -0500 Terry Bowman <terry.bowman@amd.com> wrote:
> The CXL error handler currently only logs endpoint RAS status. The CXL > topology includes several components providing RAS details to be logged > during error handling.[1] Update the current handler's RAS logging to use a > RAS register address. This will allow for adding support to log other CXL > component's RAS details in the future. > > [1] CXL3.0 Table 8-22 CXL_Capability_ID Assignment > > Co-developed-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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