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    SubjectRe: [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery
    On Tue, 23 May 2023 18:22:08 -0500
    Terry Bowman <terry.bowman@amd.com> wrote:

    > Restricted CXL host (RCH) downstream port AER information is not currently
    > logged while in the error state. One problem preventing the error logging
    > is the AER and RAS registers are not accessible. The CXL driver requires
    > changes to find RCH downstream port AER and RAS registers for purpose of
    > error logging.
    >
    > RCH downstream ports are not enumerated during a PCI bus scan and are
    > instead discovered using system firmware, ACPI in this case.[1] The
    > downstream port is implemented as a Root Complex Register Block (RCRB).
    > The RCRB is a 4k memory block containing PCIe registers based on the PCIe
    > root port.[2] The RCRB includes AER extended capability registers used for
    > reporting errors. Note, the RCH's AER Capability is located in the RCRB
    > memory space instead of PCI configuration space, thus its register access
    > is different. Existing kernel PCIe AER functions can not be used to manage
    > the downstream port AER capabilities and RAS registers because the port was
    > not enumerated during PCI scan and the registers are not PCI config
    > accessible.
    >
    > Discover RCH downstream port AER extended capability registers. Use MMIO
    > accesses to search for extended AER capability in RCRB register space.
    >
    > [1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy
    > [2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB
    >
    > Co-developed-by: Robert Richter <rrichter@amd.com>
    > Signed-off-by: Robert Richter <rrichter@amd.com>
    > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
    Seems reasonable.

    Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

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