lkml.org 
[lkml]   [2023]   [May]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH net-next v3 4/6] net: phy: microchip_t1s: fix reset complete status handling
On Fri, May 26, 2023 at 06:00:08AM +0000, Parthiban.Veerasooran@microchip.com wrote:
> Hi Ramon,
> >> + /* Read STS2 register and check for the Reset Complete status to do the
> >> + * init configuration. If the Reset Complete is not set, wait for 5us
> >> + * and then read STS2 register again and check for Reset Complete status.
> >> + * Still if it is failed then declare PHY reset error or else proceed
> >> + * for the PHY initial register configuration.
> >> + */
> >
> > This comment explains exactly what the code does, which is also obvious
> > from reading the code. A meaningful comment would be explaining why the
> > state can change 5us later.
> >
> As per design, LAN867x reset to be completed by 3us. Just for a safer
> side it is recommended to use 5us. With the assumption of more than 3us
> completion, the first read checks for the Reset Complete. If the
> config_init is more faster, then once again checks for it after 5us.
>
> As you mentioned, can we remove the existing block comment as it
> explains the code and add the above comment to explain 5us delay.
> What is your opinion on this proposal?
>
> Best Regards,
> Parthiban V
>

I'd suggest the following
/*The chip completes a reset in 3us, we might get here earlier than that,
as an added margin we'll conditionally sleep 5us*/

\
 
 \ /
  Last update: 2023-05-26 09:15    [W:0.733 / U:0.684 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site