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    SubjectRe: [PATCH v13 07/10] drm/msm/dpu: always clear every individual pending flush mask
    On 2023-05-22 17:00:36, Kuogee Hsieh wrote:
    > There are two tiers of pending flush control, top levle and

    levle -> level

    > individual hardware block. Currently only the top level of
    > flush mask is reset to 0 but the individual pending flush masks
    > of particular hardware blocks are left at their previous values,
    > eventually accumulating all possible bit values and typically
    > flushing more than necessary.
    > Reset all individual hardware blocks flush masks to 0 to avoid

    block, drop -s, because masks is plural.

    > individual hardware block be triggered accidentally.

    be = from being

    triggered = flushed?

    (You just said "individual hardware block", it would be okay to refer to
    that with just "Reset all individual hardware block flush masks to 0 to
    avoid accidentally flushing them.")

    >
    > Changes in V13:
    > -- rewording commi ttext

    commit text

    > -- add an empty space line as suggested
    >
    > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
    > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

    So no fixes tag?

    - Marijn

    > ---
    > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++
    > 1 file changed, 3 insertions(+)
    >
    > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    > index 69d0ea2..64c21e0 100644
    > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    > @@ -100,6 +100,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
    > trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
    > dpu_hw_ctl_get_flush_register(ctx));
    > ctx->pending_flush_mask = 0x0;
    > + ctx->pending_intf_flush_mask = 0;
    > + ctx->pending_wb_flush_mask = 0;
    > + ctx->pending_merge_3d_flush_mask = 0;
    >
    > memset(ctx->pending_dspp_flush_mask, 0,
    > sizeof(ctx->pending_dspp_flush_mask));
    > --
    > 2.7.4
    >

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