lkml.org 
[lkml]   [2023]   [May]   [22]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v13 07/10] drm/msm/dpu: always clear every individual pending flush mask
    Date
    There are two tiers of pending flush control, top levle and
    individual hardware block. Currently only the top level of
    flush mask is reset to 0 but the individual pending flush masks
    of particular hardware blocks are left at their previous values,
    eventually accumulating all possible bit values and typically
    flushing more than necessary.
    Reset all individual hardware blocks flush masks to 0 to avoid
    individual hardware block be triggered accidentally.

    Changes in V13:
    -- rewording commi ttext
    -- add an empty space line as suggested

    Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
    Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
    ---
    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++
    1 file changed, 3 insertions(+)

    diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    index 69d0ea2..64c21e0 100644
    --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
    @@ -100,6 +100,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
    trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
    dpu_hw_ctl_get_flush_register(ctx));
    ctx->pending_flush_mask = 0x0;
    + ctx->pending_intf_flush_mask = 0;
    + ctx->pending_wb_flush_mask = 0;
    + ctx->pending_merge_3d_flush_mask = 0;

    memset(ctx->pending_dspp_flush_mask, 0,
    sizeof(ctx->pending_dspp_flush_mask));
    --
    2.7.4
    \
     
     \ /
      Last update: 2023-05-23 02:39    [W:4.069 / U:1.044 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site