Messages in this thread | | | Date | Sun, 21 May 2023 16:43:56 +0300 | From | Vladimir Oltean <> | Subject | Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock |
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On Sat, May 20, 2023 at 06:06:03PM +0200, David Epping wrote: > +/* For VSC8501 and VSC8502 the RGMII RX clock output is disabled by default. */ > +static int vsc85xx_rgmii_enable_rx_clk(struct phy_device *phydev, > + u32 rgmii_cntl) > +{ > + int rc, phy_id; > + > + phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; > + if (PHY_ID_VSC8501 != phy_id && PHY_ID_VSC8502 != phy_id) > + return 0;
Not only bit 11 is reserved for VSC8530, but it's also read-only, so it should not matter what is written there.
Since vsc85xx_rgmii_enable_rx_clk() and vsc85xx_rgmii_set_skews() write to the same register, would it not make sense to combine the two into a single phy_modify_paged() call, and to zeroize bit 11 as part of that?
The other caller of vsc85xx_rgmii_set_skews(), VSC8572, unfortunately does not document bit 11 at all - it doesn't say if it's read-only or not. We could conditionally include the VSC8502_RGMII_RX_CLK_DISABLE bit in the "mask" argument of phy_modify_paged() based on rgmii_cntl == VSC8502_RGMII_CNTL, such as to exclude VSC8572.
What do you think?
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