Messages in this thread |  | | Date | Tue, 16 May 2023 08:13:23 -0500 | | From | Nishanth Menon <> | | Subject | Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe |
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On 11:52-20230516, Achal Verma wrote: > From: Matt Ranostay <mranostay@ti.com> > > J7200 has a limited 2x support for PCIe, and the properties should be > updated as such. >
What commit does this fix?
> Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Achal Verma <a-verma1@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > index ef352e32f19d..5e62b431d6e8 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 { > device_type = "pci"; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck"; > @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 { > interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; > ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; > max-link-speed = <3>; > - num-lanes = <4>; > + num-lanes = <2>; > power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 240 6>; > clock-names = "fck"; > -- > 2.25.1 >
-- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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