Messages in this thread | | | Date | Wed, 17 May 2023 08:55:44 +0530 | Subject | Re: [PATCH v2] usb: dwc3: core: set force_gen1 bit in USB31 devices if max speed is SS | From | Krishna Kurapati PSSNV <> |
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On 5/17/2023 6:00 AM, Thinh Nguyen wrote: > On Wed, May 17, 2023, Thinh Nguyen wrote: >> On Sun, May 14, 2023, Krishna Kurapati wrote: >>> Currently for dwc3_usb31 controller, if maximum_speed is limited to >>> super-speed in DT, then device mode is limited to SS, but host mode >>> still works in SSP. >>> >>> The documentation for max-speed property is as follows: >>> >>> "Tells USB controllers we want to work up to a certain speed. >>> Incase this isn't passed via DT, USB controllers should default to >>> their maximum HW capability." >>> >>> It doesn't specify that the property is only for device mode. >>> There are cases where we need to limit the host's maximum speed to >>> SuperSpeed only. Use this property for host mode to contrain host's >>> speed to SuperSpeed. >>> >>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >>> --- >>> Link to v1: https://urldefense.com/v3/__https://lore.kernel.org/all/20230512170107.18821-1-quic_kriskura@quicinc.com/__;!!A4F2R9G_pg!dCg_3WK2oNXNb6d0a_VuyjkeeZJTU1aY4dik6g35XB7mtG7EJeR1uPMfxFja49OfXp7Yhsg1yqjnylCYYEg7YCAhqfAZ0Q$ >>> >>> Discussion regarding the same at: >>> https://urldefense.com/v3/__https://lore.kernel.org/all/e465c69c-3a9d-cbdb-d44e-96b99cfa1a92@quicinc.com/__;!!A4F2R9G_pg!dCg_3WK2oNXNb6d0a_VuyjkeeZJTU1aY4dik6g35XB7mtG7EJeR1uPMfxFja49OfXp7Yhsg1yqjnylCYYEg7YCDRLUrJWg$ >>> >>> drivers/usb/dwc3/core.c | 8 ++++++++ >>> drivers/usb/dwc3/core.h | 5 +++++ >>> 2 files changed, 13 insertions(+) >>> >>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >>> index 278cd1c33841..33bc72595e74 100644 >>> --- a/drivers/usb/dwc3/core.c >>> +++ b/drivers/usb/dwc3/core.c >>> @@ -1262,6 +1262,14 @@ static int dwc3_core_init(struct dwc3 *dwc) >>> } >>> } >>> >>> + if ((hw_mode != DWC3_GHWPARAMS0_MODE_GADGET) && >>> + (DWC3_IP_IS(DWC31)) && >>> + (dwc->maximum_speed == USB_SPEED_SUPER)) { >>> + reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); >>> + reg |= DWC3_LLUCTL_FORCE_GEN1; >>> + dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); >>> + } >>> + >> >> Perhaps this should be done for every usb3 port rather than just the >> port_0. This patch can go after your multi-port series is added to >> Greg's branch where you can check for number of usb3 ports. >> > > Can you also add dwc_usb32 settings? It should look something like this: > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 0beaab932e7d..4bd2564aa163 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -1262,6 +1262,40 @@ static int dwc3_core_init(struct dwc3 *dwc) > } > } > > + if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET) { > + int i; > + > + if (DWC3_IP_IS(DWC31) && > + dwc->maximum_speed == USB_SPEED_SUPER) { > + for (i = 0; i < dwc->num_usb3_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i)); > + reg |= DWC3_LLUCTL_FORCE_GEN1; > + dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg); > + } > + } > + > + if (DWC3_IP_IS(DWC32) && > + dwc->max_ssp_rate != USB_SSP_GEN_2x2) { > + int lsr_speed = -EINVAL; > + > + if (dwc->maximum_speed == USB_SPEED_SUPER) > + lsr_speed = DWC3_LCSR_GEN_1x1; > + else if (dwc->max_ssp_rate == USB_SSP_GEN_2x1) > + lsr_speed = DWC3_LCSR_GEN_2x1; > + else if (dwc->max_ssp_rate == USB_SSP_GEN_1x2) > + lsr_speed = DWC3_LCSR_GEN_1x2; > + > + if (lsr_speed != -EINVAL) { > + for (i = 0; i < dwc->num_usb3_ports; i++) { > + reg = dwc3_readl(dwc->regs, DWC3_LCSR_USB32CTL(i)); > + reg &= ~DWC3_LCSR_USB32CTL_SPEED_MASK; > + reg |= lsr_speed; > + dwc3_writel(dwc->regs, DWC3_LCSR_USB32CTL(i), reg); > + } > + } > + } > + } > + > return 0; > > err_power_off_phy: > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index d56457c02996..415e0215fe00 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -170,6 +170,9 @@ > #define DWC3_OEVTEN 0xcc0C > #define DWC3_OSTS 0xcc10 > > +#define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80)) > +#define DWC3_LCSR_USB32CTL(n) (0xd07c + ((n) * 0x80)) > + > /* Bit fields */ > > /* Global SoC Bus Configuration INCRx Register 0 */ > @@ -653,6 +656,16 @@ > #define DWC3_OSTS_VBUSVLD BIT(1) > #define DWC3_OSTS_CONIDSTS BIT(0) > > +/* LLUCTL Register */ > +#define DWC3_LLUCTL_FORCE_GEN1 BIT(10) > + > +/* LCSR_USB32CTL Register */ > +#define DWC3_LCSR_USB32CTL_SPEED_MASK 0x3 > +#define DWC3_LCSR_GEN_1x1 0 > +#define DWC3_LCSR_GEN_1x2 1 > +#define DWC3_LCSR_GEN_2x1 2 > +#define DWC3_LCSR_GEN_2x2 3 > + > /* Structures */ > > struct dwc3_trb; > > -- > > Thanks, > Thinh
Hi Thinh,
Sure, will split it up into two patches and send as a series. But might need your help in testing SSP patch as I don't have any device supporting ssp.
Regards, Krishna,
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