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SubjectRe: [PATCH V11 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant
On 2023-04-04 11:16, Devi Priya wrote:
> Add initial device tree support for Qualcomm IPQ9574 SoC and
> Reference Design Platform(RDP) 433 which is based on IPQ9574
> family of SoCs
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
> Changes in V11:
> - Dropped the unused backup clock source bias_pll_ubi_nc_clk
>
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 84 +++++++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 263 ++++++++++++++++++++
> 3 files changed, 348 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>

[...]

> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + reg = <0x0b000000 0x1000>, /* GICD */
> + <0x0b002000 0x1000>, /* GICC */

This is definitely wrong. The GICC region cannot be less than
8kB, as the GICC_DIR register is in the second 4kB region.

I'm pretty sure the kernel shouts at you when booting at EL2.

> + <0x0b001000 0x1000>, /* GICH */
> + <0x0b004000 0x1000>; /* GICV */

Same thing here.

> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

Missing target CPU encoding.

M.
--
Jazz is not dead. It just smells funny...

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