Messages in this thread | | | Date | Fri, 14 Apr 2023 15:26:52 +0300 | Subject | Re: [PATCH net] net: dsa: mt7530: permit port 5 to work without port 6 on MT7621 SoC | From | Arınç ÜNAL <> |
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On 7.03.2023 18:54, Vladimir Oltean wrote: > The MT7530 switch from the MT7621 SoC has 2 ports which can be set up as > internal: port 5 and 6. Arınç reports that the GMAC1 attached to port 5 > receives corrupted frames, unless port 6 (attached to GMAC0) has been > brought up by the driver. This is true regardless of whether port 5 is > used as a user port or as a CPU port (carrying DSA tags). > > Offline debugging (blind for me) which began in the linked thread showed > experimentally that the configuration done by the driver for port 6 > contains a step which is needed by port 5 as well - the write to > CORE_GSWPLL_GRP2 (note that I've no idea as to what it does, apart from > the comment "Set core clock into 500Mhz"). Prints put by Arınç show that > the reset value of CORE_GSWPLL_GRP2 is RG_GSWPLL_POSDIV_500M(1) | > RG_GSWPLL_FBKDIV_500M(40) (0x128), both on the MCM MT7530 from the > MT7621 SoC, as well as on the standalone MT7530 from MT7623NI Bananapi > BPI-R2. Apparently, port 5 on the standalone MT7530 can work under both > values of the register, while on the MT7621 SoC it cannot.
I finally found out why. Looking at gsw_mt7623.c [0], setting the core clock into 500Mhz is done for 40MHz XTAL. With some dev_info code, I was able to confirm that the MCM MT7530 on my MT7621 board runs at 40MHz whilst the standalone MT7530 on my Bananapi BPI-R2 runs at 25MHz.
[0] https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/master/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
Arınç
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