Messages in this thread | | | From | <> | Subject | Re: [PATCH v2 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver | Date | Fri, 14 Apr 2023 23:08:16 +0000 |
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On Thu, 2023-04-13 at 22:50 -0700, Christoph Hellwig wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > > know the content is safe > > > > On Thu, Apr 13, 2023 at 10:40:41PM +0000, > > > Kelvin.Cao@microchip.com wrote: > > > > > > > > Why is the lock needed while reading the status and > > > > > > > > waiting > > > > > > > > for it with long delays? > > > > There's (low) chance of access to the same ctrl register from > > > > other > > > > paths which might change the value of status in an unexpected > > > > way. > > It > > > > also prevents the hardware operation from being interrupted > > > > until > > it > > > > indicates it has finished by a bit set in the status register. > > > > Well, the lock is obviously required to protecte the reads to the > > register. But why do you need to hold the lock over the reads and > > the delay?
I wanted to protect the complete hardware operation, from kick-off by ctrl writing to status change indicating completion, which might involves delays in between when more than 1 status checks required.
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