Messages in this thread | | | Date | Tue, 7 Mar 2023 12:12:07 +0530 | Subject | Re: [PATCH 05/11] dt-bindings: clock: qcom: gcc-ipq9574: Add Q6 gcc clock control | From | Sricharan Ramabadhran <> |
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On 3/7/2023 10:11 AM, Manikanta Mylavarapu wrote: > Add support for the QDSP6 gcc clock control used on IPQ9574 > based devices. This would allow mpd remoteproc driver to control > the required gcc clocks to bring the subsystem out of reset. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > --- > include/dt-bindings/clock/qcom,ipq9574-gcc.h | 159 ++++++++++--------- > 1 file changed, 83 insertions(+), 76 deletions(-) > > diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h > index c89e96d568c6..8bd6350ecd56 100644 > --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h > +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h > @@ -138,80 +138,87 @@ > #define WCSS_AHB_CLK_SRC 129 > #define GCC_Q6_AHB_CLK 130 > #define GCC_Q6_AHB_S_CLK 131 > -#define GCC_WCSS_ECAHB_CLK 132 > -#define GCC_WCSS_ACMT_CLK 133 > -#define GCC_SYS_NOC_WCSS_AHB_CLK 134 > -#define WCSS_AXI_M_CLK_SRC 135 > -#define GCC_ANOC_WCSS_AXI_M_CLK 136 > -#define QDSS_AT_CLK_SRC 137 > -#define GCC_Q6SS_ATBM_CLK 138 > -#define GCC_WCSS_DBG_IFC_ATB_CLK 139 > -#define GCC_NSSNOC_ATB_CLK 140 > -#define GCC_QDSS_AT_CLK 141 > -#define GCC_SYS_NOC_AT_CLK 142 > -#define GCC_PCNOC_AT_CLK 143 > -#define GCC_USB0_EUD_AT_CLK 144 > -#define GCC_QDSS_EUD_AT_CLK 145 > -#define QDSS_STM_CLK_SRC 146 > -#define GCC_QDSS_STM_CLK 147 > -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 148 > -#define QDSS_TRACECLKIN_CLK_SRC 149 > -#define GCC_QDSS_TRACECLKIN_CLK 150 > -#define QDSS_TSCTR_CLK_SRC 151 > -#define GCC_Q6_TSCTR_1TO2_CLK 152 > -#define GCC_WCSS_DBG_IFC_NTS_CLK 153 > -#define GCC_QDSS_TSCTR_DIV2_CLK 154 > -#define GCC_QDSS_TS_CLK 155 > -#define GCC_QDSS_TSCTR_DIV4_CLK 156 > -#define GCC_NSS_TS_CLK 157 > -#define GCC_QDSS_TSCTR_DIV8_CLK 158 > -#define GCC_QDSS_TSCTR_DIV16_CLK 159 > -#define GCC_Q6SS_PCLKDBG_CLK 160 > -#define GCC_Q6SS_TRIG_CLK 161 > -#define GCC_WCSS_DBG_IFC_APB_CLK 162 > -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 163 > -#define GCC_QDSS_DAP_CLK 164 > -#define GCC_QDSS_APB2JTAG_CLK 165 > -#define GCC_QDSS_TSCTR_DIV3_CLK 166 > -#define QPIC_IO_MACRO_CLK_SRC 167 > -#define GCC_QPIC_IO_MACRO_CLK 168 > -#define Q6_AXI_CLK_SRC 169 > -#define GCC_Q6_AXIM_CLK 170 > -#define GCC_WCSS_Q6_TBU_CLK 171 > -#define GCC_MEM_NOC_Q6_AXI_CLK 172 > -#define Q6_AXIM2_CLK_SRC 173 > -#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 174 > -#define GCC_NSSNOC_MEMNOC_CLK 175 > -#define GCC_NSSNOC_MEM_NOC_1_CLK 176 > -#define GCC_NSS_TBU_CLK 177 > -#define GCC_MEM_NOC_NSSNOC_CLK 178 > -#define LPASS_AXIM_CLK_SRC 179 > -#define LPASS_SWAY_CLK_SRC 180 > -#define ADSS_PWM_CLK_SRC 181 > -#define GCC_ADSS_PWM_CLK 182 > -#define GP1_CLK_SRC 183 > -#define GP2_CLK_SRC 184 > -#define GP3_CLK_SRC 185 > -#define DDRSS_SMS_SLOW_CLK_SRC 186 > -#define GCC_XO_CLK_SRC 187 > -#define GCC_XO_CLK 188 > -#define GCC_NSSNOC_QOSGEN_REF_CLK 189 > -#define GCC_NSSNOC_TIMEOUT_REF_CLK 190 > -#define GCC_XO_DIV4_CLK 191 > -#define GCC_UNIPHY0_SYS_CLK 192 > -#define GCC_UNIPHY1_SYS_CLK 193 > -#define GCC_UNIPHY2_SYS_CLK 194 > -#define GCC_CMN_12GPLL_SYS_CLK 195 > -#define GCC_NSSNOC_XO_DCD_CLK 196 > -#define GCC_Q6SS_BOOT_CLK 197 > -#define UNIPHY_SYS_CLK_SRC 198 > -#define NSS_TS_CLK_SRC 199 > -#define GCC_ANOC_PCIE0_1LANE_M_CLK 200 > -#define GCC_ANOC_PCIE1_1LANE_M_CLK 201 > -#define GCC_ANOC_PCIE2_2LANE_M_CLK 202 > -#define GCC_ANOC_PCIE3_2LANE_M_CLK 203 > -#define GCC_SNOC_PCIE0_1LANE_S_CLK 204 > -#define GCC_SNOC_PCIE1_1LANE_S_CLK 205 > -#define GCC_SNOC_PCIE2_2LANE_S_CLK 206 > -#define GCC_SNOC_PCIE3_2LANE_S_CLK 207 > +#define GCC_WCSS_AHB_S_CLK 132 > +#define GCC_WCSS_ECAHB_CLK 133 > +#define GCC_WCSS_ACMT_CLK 134 > +#define GCC_SYS_NOC_WCSS_AHB_CLK 135 > +#define WCSS_AXI_M_CLK_SRC 136 > +#define GCC_WCSS_AXI_M_CLK 137 > +#define GCC_ANOC_WCSS_AXI_M_CLK 138 > +#define QDSS_AT_CLK_SRC 139 > +#define GCC_Q6SS_ATBM_CLK 140 > +#define GCC_WCSS_DBG_IFC_ATB_CLK 141 > +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 142 > +#define GCC_NSSNOC_ATB_CLK 143 > +#define GCC_QDSS_AT_CLK 144 > +#define GCC_SYS_NOC_AT_CLK 145 > +#define GCC_PCNOC_AT_CLK 146 > +#define GCC_USB0_EUD_AT_CLK 147 > +#define GCC_QDSS_EUD_AT_CLK 148 > +#define QDSS_STM_CLK_SRC 149 > +#define GCC_QDSS_STM_CLK 150 > +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 151 > +#define QDSS_TRACECLKIN_CLK_SRC 152 > +#define GCC_QDSS_TRACECLKIN_CLK 153 > +#define QDSS_TSCTR_CLK_SRC 154 > +#define GCC_Q6_TSCTR_1TO2_CLK 155 > +#define GCC_WCSS_DBG_IFC_NTS_CLK 156 > +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 157 > +#define GCC_QDSS_TSCTR_DIV2_CLK 158 > +#define GCC_QDSS_TS_CLK 159 > +#define GCC_QDSS_TSCTR_DIV4_CLK 160 > +#define GCC_NSS_TS_CLK 161 > +#define GCC_QDSS_TSCTR_DIV8_CLK 162 > +#define GCC_QDSS_TSCTR_DIV16_CLK 163 > +#define GCC_Q6SS_PCLKDBG_CLK 164 > +#define GCC_Q6SS_TRIG_CLK 165 > +#define GCC_WCSS_DBG_IFC_APB_CLK 166 > +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 167 > +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 168 > +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 169 > +#define GCC_QDSS_DAP_CLK 170 > +#define GCC_QDSS_APB2JTAG_CLK 171 > +#define GCC_QDSS_TSCTR_DIV3_CLK 172 > +#define QPIC_IO_MACRO_CLK_SRC 173 > +#define GCC_QPIC_IO_MACRO_CLK 174 > +#define Q6_AXI_CLK_SRC 175 > +#define GCC_Q6_AXIM_CLK 176 > +#define GCC_Q6_AXIM2_CLK 177 > +#define GCC_WCSS_Q6_TBU_CLK 178 > +#define GCC_MEM_NOC_Q6_AXI_CLK 179 > +#define Q6_AXIM2_CLK_SRC 180 > +#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 181 > +#define GCC_NSSNOC_MEMNOC_CLK 182 > +#define GCC_NSSNOC_MEM_NOC_1_CLK 183 > +#define GCC_NSS_TBU_CLK 184 > +#define GCC_MEM_NOC_NSSNOC_CLK 185 > +#define LPASS_AXIM_CLK_SRC 186 > +#define LPASS_SWAY_CLK_SRC 187 > +#define ADSS_PWM_CLK_SRC 188 > +#define GCC_ADSS_PWM_CLK 189 > +#define GP1_CLK_SRC 190 > +#define GP2_CLK_SRC 191 > +#define GP3_CLK_SRC 192 > +#define DDRSS_SMS_SLOW_CLK_SRC 193 > +#define GCC_XO_CLK_SRC 194 > +#define GCC_XO_CLK 195 > +#define GCC_NSSNOC_QOSGEN_REF_CLK 196 > +#define GCC_NSSNOC_TIMEOUT_REF_CLK 197 > +#define GCC_XO_DIV4_CLK 198 > +#define GCC_UNIPHY0_SYS_CLK 199 > +#define GCC_UNIPHY1_SYS_CLK 200 > +#define GCC_UNIPHY2_SYS_CLK 201 > +#define GCC_CMN_12GPLL_SYS_CLK 202 > +#define GCC_NSSNOC_XO_DCD_CLK 203 > +#define GCC_Q6SS_BOOT_CLK 204 > +#define UNIPHY_SYS_CLK_SRC 205 > +#define NSS_TS_CLK_SRC 206 > +#define GCC_ANOC_PCIE0_1LANE_M_CLK 207 > +#define GCC_ANOC_PCIE1_1LANE_M_CLK 208 > +#define GCC_ANOC_PCIE2_2LANE_M_CLK 209 > +#define GCC_ANOC_PCIE3_2LANE_M_CLK 210 > +#define GCC_SNOC_PCIE0_1LANE_S_CLK 211 > +#define GCC_SNOC_PCIE1_1LANE_S_CLK 212 > +#define GCC_SNOC_PCIE2_2LANE_S_CLK 213 > +#define GCC_SNOC_PCIE3_2LANE_S_CLK 214
These should be added in the end as new entries.
Regards, Sricharan
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