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    SubjectRe: [PATCH v3 14/34] microblaze: Implement the new page table range API
    On Tue, Feb 28, 2023 at 09:37:17PM +0000, Matthew Wilcox (Oracle) wrote:
    > Add set_ptes(), update_mmu_cache_range(), flush_icache_pages() and
    > flush_dcache_folio(). Also change the calling convention for set_pte()
    > to be the same as other architectures.
    >
    > Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
    > Cc: Michal Simek <monstr@monstr.eu>
    > ---
    > arch/microblaze/include/asm/cacheflush.h | 8 ++++++++
    > arch/microblaze/include/asm/pgtable.h | 17 ++++++++++++-----
    > arch/microblaze/include/asm/tlbflush.h | 4 +++-
    > 3 files changed, 23 insertions(+), 6 deletions(-)
    >
    > diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
    > index 39f8fb6768d8..e6641ff98cb3 100644
    > --- a/arch/microblaze/include/asm/cacheflush.h
    > +++ b/arch/microblaze/include/asm/cacheflush.h
    > @@ -74,6 +74,14 @@ do { \
    > flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
    > } while (0);
    >
    > +static void flush_dcache_folio(struct folio *folio)
    > +{
    > + unsigned long addr = folio_pfn(folio) << PAGE_SHIFT;
    > +
    > + flush_dcache_range(addr, addr + folio_size(folio));
    > +}
    > +#define flush_dcache_folio flush_dcache_folio
    > +
    > #define flush_cache_page(vma, vmaddr, pfn) \
    > flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE);
    >
    > diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
    > index d1b8272abcd9..a01e1369b486 100644
    > --- a/arch/microblaze/include/asm/pgtable.h
    > +++ b/arch/microblaze/include/asm/pgtable.h
    > @@ -330,18 +330,25 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr,
    > /*
    > * set_pte stores a linux PTE into the linux page table.
    > */
    > -static inline void set_pte(struct mm_struct *mm, unsigned long addr,
    > - pte_t *ptep, pte_t pte)
    > +static inline void set_pte(pte_t *ptep, pte_t pte)
    > {
    > *ptep = pte;
    > }
    >
    > -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
    > - pte_t *ptep, pte_t pte)
    > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
    > + pte_t *ptep, pte_t pte, unsigned int nr)
    > {
    > - *ptep = pte;
    > + for (;;) {
    > + set_pte(ptep, pte);
    > + if (--nr == 0)
    > + break;
    > + ptep++;
    > + pte_val(pte) += 1 << PFN_SHIFT_OFFSET;

    This is the same as

    pte_val(pte) += PAGE_SIZE;

    isn't it?

    > + }
    > }
    >
    > +#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
    > +
    > #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
    > static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
    > unsigned long address, pte_t *ptep)
    > diff --git a/arch/microblaze/include/asm/tlbflush.h b/arch/microblaze/include/asm/tlbflush.h
    > index 2038168ed128..1b179e5e9062 100644
    > --- a/arch/microblaze/include/asm/tlbflush.h
    > +++ b/arch/microblaze/include/asm/tlbflush.h
    > @@ -33,7 +33,9 @@ static inline void local_flush_tlb_range(struct vm_area_struct *vma,
    >
    > #define flush_tlb_kernel_range(start, end) do { } while (0)
    >
    > -#define update_mmu_cache(vma, addr, ptep) do { } while (0)
    > +#define update_mmu_cache_range(vma, addr, ptep, nr) do { } while (0)
    > +#define update_mmu_cache(vma, addr, pte) \
    > + update_mmu_cache_range(vma, addr, ptep, 1)
    >
    > #define flush_tlb_all local_flush_tlb_all
    > #define flush_tlb_mm local_flush_tlb_mm
    > --
    > 2.39.1
    >
    >

    --
    Sincerely yours,
    Mike.

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