Messages in this thread | | | Date | Tue, 7 Feb 2023 09:45:44 +0100 | Subject | Re: [PATCH v1 05/45] clk: mediatek: mt2712: Migrate topckgen/mcucfg to mtk_clk_simple_probe() | From | AngeloGioacchino Del Regno <> |
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Il 07/02/23 07:15, Chen-Yu Tsai ha scritto: > On Mon, Feb 6, 2023 at 11:29 PM AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> wrote: >> >> Now that the common mtk_clk_simple_{probe,remove}() functions can deal >> with divider clocks it is possible to migrate more clock drivers to it: >> in this case, it's about topckgen. >> While at it, also perform a fast migration for mcucfg. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > >> --- >> drivers/clk/mediatek/clk-mt2712.c | 127 +++++------------------------- >> 1 file changed, 21 insertions(+), 106 deletions(-) >>
..snip.. __func__, r); >> +static const struct mtk_clk_desc topck_desc = { >> + .clks = top_clks, >> + .num_clks = ARRAY_SIZE(top_clks), >> + .fixed_clks = top_fixed_clks, >> + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), >> + .factor_clks = top_divs, >> + .num_factor_clks = ARRAY_SIZE(top_divs), >> + .composite_clks = top_muxes, >> + .num_composite_clks = ARRAY_SIZE(top_muxes), >> + .divider_clks = top_adj_divs, >> + .num_divider_clks = ARRAY_SIZE(top_adj_divs), >> + .clk_lock = &mt2712_clk_lock, > > At some point maybe we should look into splitting up the locks to one > per block, or converting everything to regmap. >
I was thinking the same about the locks... but about regmap, that would actually add up some overhead at every R/W operation and I would really like to measure that precisely before doing any kind of regmap conversion for the MediaTek clocks.
Perhaps I'll even find a way to avoid any kind of (even if small) overhead while doing that sometime in the future, which wouldn't be benefitting only MediaTek, but also other users like Qualcomm (as they have practically all clocks on regmap!).
Cheers, Angelo
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