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    Subject[PATCH v8 08/11] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
    Date
    Add the SM8550 both g4 and g3 configurations. In addition, there is a
    new "lane shared" table that needs to be configured for g4, along with
    the No-CSR list of resets. The no-CSR allows resetting the PHY without
    actually dropping the PHY configuration. The no-CSR needs to be
    deasserted only after the PHY has been configured and the PLL has
    stabilized.

    Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
    Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
    Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
    Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    ---

    The v7 of this patch is:
    https://lore.kernel.org/all/20230203081807.2248625-9-abel.vesa@linaro.org/

    Changes since v7:
    * Added more info to the commit message about the no-CSR resets
    * Moved all ln_shrd related struct members after pcs_misc, like Johan
    suggested
    * Padded the tx to 4 digits in v6.20 offsets, like Johan suggested
    * Dropped the no-CSR reset bulk and used single reset instead, also
    added a flag to the cfg to specify if it uses the no-CSR reset or not

    Changes since v6:
    * none

    Changes since v5:
    * renmaed the no-CSR reset to "phy_nocsr" as discussed off-list with
    Bjorn and Johan

    Changes since v4:
    * dropped _serdes infix from ln_shrd table name and from every ln_shrd
    variable name
    * added hyphen between "no CSR" in both places
    * dropped has_ln_shrd_serdes_tbl
    * reordered qmp_pcie_offsets_v6_20 by struct members
    * added rollback for no-CSR reset in qmp_pcie_init fail path
    * moved ln_shrd offset calculation after port_b

    Changes since v3:
    * added Dmitry's R-b tag

    Changes since v2:
    * none

    Changes since v1:
    * split all the offsets into separate patches, like Vinod suggested



    drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 344 ++++++++++++++++++++++-
    1 file changed, 343 insertions(+), 1 deletion(-)

    diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
    index 907f3f236f05..ca9a443b7c08 100644
    --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
    +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
    @@ -1506,6 +1506,234 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] =
    QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
    };

    +static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
    + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
    + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
    + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
    + QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
    + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
    + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
    + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
    + QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
    + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
    + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
    + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
    + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
    +};
    +
    +static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
    + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
    +};
    +
    struct qmp_pcie_offsets {
    u16 serdes;
    u16 pcs;
    @@ -1514,6 +1742,7 @@ struct qmp_pcie_offsets {
    u16 rx;
    u16 tx2;
    u16 rx2;
    + u16 ln_shrd;
    };

    struct qmp_phy_cfg_tbls {
    @@ -1527,6 +1756,8 @@ struct qmp_phy_cfg_tbls {
    int pcs_num;
    const struct qmp_phy_init_tbl *pcs_misc;
    int pcs_misc_num;
    + const struct qmp_phy_init_tbl *ln_shrd;
    + int ln_shrd_num;
    };

    /* struct qmp_phy_cfg - per-PHY initialization config */
    @@ -1569,6 +1800,8 @@ struct qmp_phy_cfg {

    bool skip_start_delay;

    + bool has_nocsr_reset;
    +
    /* QMP PHY pipe clock interface rate */
    unsigned long pipe_clock_rate;
    };
    @@ -1586,6 +1819,7 @@ struct qmp_pcie {
    void __iomem *rx;
    void __iomem *tx2;
    void __iomem *rx2;
    + void __iomem *ln_shrd;

    void __iomem *port_b;

    @@ -1594,6 +1828,7 @@ struct qmp_pcie {
    int num_pipe_clks;

    struct reset_control_bulk_data *resets;
    + struct reset_control *nocsr_reset;
    struct regulator_bulk_data *vregs;

    struct phy *phy;
    @@ -1648,6 +1883,10 @@ static const char * const qmp_phy_vreg_l[] = {
    "vdda-phy", "vdda-pll",
    };

    +static const char * const sm8550_qmp_phy_vreg_l[] = {
    + "vdda-phy", "vdda-pll", "vdda-qref",
    +};
    +
    /* list of resets */
    static const char * const ipq8074_pciephy_reset_l[] = {
    "phy", "common",
    @@ -1667,6 +1906,17 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
    .rx2 = 0x1800,
    };

    +static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
    + .serdes = 0x1000,
    + .pcs = 0x1200,
    + .pcs_misc = 0x1400,
    + .tx = 0x0000,
    + .rx = 0x0200,
    + .tx2 = 0x0800,
    + .rx2 = 0x0a00,
    + .ln_shrd = 0x0e00,
    +};
    +
    static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
    .lanes = 1,

    @@ -2214,6 +2464,67 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
    .phy_status = PHYSTATUS_4_20,
    };

    +static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
    + .lanes = 2,
    +
    + .offsets = &qmp_pcie_offsets_v5,
    +
    + .tbls = {
    + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
    + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
    + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
    + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
    + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
    + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
    + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
    + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
    + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
    + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
    + },
    + .clk_list = sc8280xp_pciephy_clk_l,
    + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
    + .reset_list = sdm845_pciephy_reset_l,
    + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
    + .vreg_list = qmp_phy_vreg_l,
    + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
    + .regs = pciephy_v5_regs_layout,
    +
    + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
    + .phy_status = PHYSTATUS,
    +};
    +
    +static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
    + .lanes = 2,
    +
    + .offsets = &qmp_pcie_offsets_v6_20,
    +
    + .tbls = {
    + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
    + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
    + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
    + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
    + .rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
    + .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
    + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
    + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
    + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
    + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
    + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
    + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
    + },
    + .clk_list = sc8280xp_pciephy_clk_l,
    + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
    + .reset_list = sdm845_pciephy_reset_l,
    + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
    + .vreg_list = sm8550_qmp_phy_vreg_l,
    + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
    + .regs = pciephy_v5_regs_layout,
    +
    + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
    + .phy_status = PHYSTATUS_4_20,
    + .has_nocsr_reset = true,
    +};
    +
    static void qmp_pcie_configure_lane(void __iomem *base,
    const struct qmp_phy_init_tbl tbl[],
    int num,
    @@ -2268,6 +2579,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
    void __iomem *rx2 = qmp->rx2;
    void __iomem *pcs = qmp->pcs;
    void __iomem *pcs_misc = qmp->pcs_misc;
    + void __iomem *ln_shrd = qmp->ln_shrd;

    if (!tbls)
    return;
    @@ -2289,6 +2601,8 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
    qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
    qmp_pcie_init_port_b(qmp, tbls);
    }
    +
    + qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
    }

    static int qmp_pcie_init(struct phy *phy)
    @@ -2309,12 +2623,18 @@ static int qmp_pcie_init(struct phy *phy)
    goto err_disable_regulators;
    }

    + ret = reset_control_assert(qmp->nocsr_reset);
    + if (ret) {
    + dev_err(qmp->dev, "no-csr reset assert failed\n");
    + goto err_assert_reset;
    + }
    +
    usleep_range(200, 300);

    ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
    if (ret) {
    dev_err(qmp->dev, "reset deassert failed\n");
    - goto err_disable_regulators;
    + goto err_assert_reset;
    }

    ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
    @@ -2370,6 +2690,12 @@ static int qmp_pcie_power_on(struct phy *phy)
    if (ret)
    return ret;

    + ret = reset_control_deassert(qmp->nocsr_reset);
    + if (ret) {
    + dev_err(qmp->dev, "no-csr reset deassert failed\n");
    + goto err_disable_pipe_clk;
    + }
    +
    /* Pull PHY out of reset state */
    qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);

    @@ -2503,6 +2829,13 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
    if (ret)
    return dev_err_probe(dev, ret, "failed to get resets\n");

    + if (cfg->has_nocsr_reset) {
    + qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
    + if (IS_ERR(qmp->nocsr_reset))
    + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
    + "failed to get no-CSR reset\n");
    + }
    +
    return 0;
    }

    @@ -2725,6 +3058,9 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
    return PTR_ERR(qmp->port_b);
    }

    + if (cfg->tbls.ln_shrd)
    + qmp->ln_shrd = base + offs->ln_shrd;
    +
    qmp->num_pipe_clks = 2;
    qmp->pipe_clks[0].id = "pipe";
    qmp->pipe_clks[1].id = "pipediv2";
    @@ -2865,6 +3201,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
    }, {
    .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
    .data = &sm8450_qmp_gen4x2_pciephy_cfg,
    + }, {
    + .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
    + .data = &sm8550_qmp_gen3x2_pciephy_cfg,
    + }, {
    + .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
    + .data = &sm8550_qmp_gen4x2_pciephy_cfg,
    },
    { },
    };
    --
    2.34.1
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      Last update: 2023-03-27 00:11    [W:4.867 / U:0.004 seconds]
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