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    Subject[PATCH AUTOSEL 6.2 39/60] drm/amd/display: fix FCLK pstate change underflow
    Date
    From: Vladimir Stempen <vladimir.stempen@amd.com>

    [ Upstream commit 972243f973eb0821084e5833d5f7f4ed025f42da ]

    [Why]
    Currently we set FCLK p-state change
    watermark calculated based on dummy
    p-state latency when UCLK p-state is
    not supported

    [How]
    Calculate FCLK p-state change watermark
    based on on FCLK pstate change latency
    in case UCLK p-state is not supported

    Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
    Acked-by: Alex Hung <alex.hung@amd.com>
    Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
    Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++++
    1 file changed, 4 insertions(+)

    diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
    index f94abd124021e..8450f59c26186 100644
    --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
    +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
    @@ -2038,6 +2038,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
    */
    context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
    context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
    + /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
    + * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
    + */
    + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
    } else {
    /* Set A:
    * All clocks min.
    --
    2.39.0
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