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    Subject[PATCH AUTOSEL 6.2 46/60] drm/amd/display: Do not commit pipe when updating DRR
    Date
    From: Wesley Chalmers <Wesley.Chalmers@amd.com>

    [ Upstream commit 8f0d304d21b351d65e8c434c5399a40231876ba1 ]

    [WHY]
    DRR and Pipe cannot be updated on
    the same frame, or else underflow will
    occur.

    Reviewed-by: Jun Lei <Jun.Lei@amd.com>
    Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
    Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++++++++++++++
    drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 3 ++-
    drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 9 +++++++++
    drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 2 ++
    .../drm/amd/display/dc/inc/hw/timing_generator.h | 1 +
    5 files changed, 29 insertions(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
    index c03e86e49fea3..698ef50e83f3f 100644
    --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
    +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
    @@ -3335,6 +3335,21 @@ static void commit_planes_for_stream(struct dc *dc,

    dc_z10_restore(dc);

    + if (update_type == UPDATE_TYPE_FULL) {
    + /* wait for all double-buffer activity to clear on all pipes */
    + int pipe_idx;
    +
    + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
    + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
    +
    + if (!pipe_ctx->stream)
    + continue;
    +
    + if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
    + pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
    + }
    + }
    +
    if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
    /* Optimize seamless boot flag keeps clocks and watermarks high until
    * first flip. After first flip, optimization is required to lower
    diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
    index 88ac5f6f4c96c..0b37bb0e184b2 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
    +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
    @@ -519,7 +519,8 @@ struct dcn_optc_registers {
    type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
    type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
    type OTG_CRC_DATA_FORMAT;\
    - type OTG_V_TOTAL_LAST_USED_BY_DRR;
    + type OTG_V_TOTAL_LAST_USED_BY_DRR;\
    + type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;

    #define TG_REG_FIELD_LIST_DCN3_2(type) \
    type OTG_H_TIMING_DIV_MODE_MANUAL;
    diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
    index 867d60151aebb..08b92715e2e64 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
    @@ -291,6 +291,14 @@ static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool e
    OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
    }

    +void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)
    +{
    + struct optc *optc1 = DCN10TG_FROM_TG(optc);
    +
    + REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */
    +
    +}
    +
    void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
    {
    optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
    @@ -360,6 +368,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
    .program_manual_trigger = optc2_program_manual_trigger,
    .setup_manual_trigger = optc2_setup_manual_trigger,
    .get_hw_timing = optc1_get_hw_timing,
    + .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
    };

    void dcn30_timing_generator_init(struct optc *optc1)
    diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
    index dd45a5499b078..fb06dc9a48937 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
    +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
    @@ -279,6 +279,7 @@
    SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
    SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
    SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
    + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
    SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
    SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh)

    @@ -317,6 +318,7 @@
    SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
    SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
    SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
    + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
    SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh)

    void dcn30_timing_generator_init(struct optc *optc1);
    diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
    index 0e42e721dd15a..1d9f9c53d2bd6 100644
    --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
    +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
    @@ -331,6 +331,7 @@ struct timing_generator_funcs {
    uint32_t vtotal_change_limit);

    void (*init_odm)(struct timing_generator *tg);
    + void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);
    };

    #endif
    --
    2.39.0
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