Messages in this thread | | | Date | Fri, 24 Feb 2023 16:09:31 -0800 | From | Josh Poimboeuf <> | Subject | Re: [PATCH v9 7/8] x86/cpu: Support AMD Automatic IBRS |
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On Fri, Feb 24, 2023 at 11:51:17PM +0100, Borislav Petkov wrote: > On Fri, Feb 24, 2023 at 10:08:32PM +0100, Borislav Petkov wrote: > > On Fri, Feb 24, 2023 at 10:52:57AM -0800, Josh Poimboeuf wrote: > > > Doesn't this only enable it on the boot CPU? > > > > Whoops, you might be right. > > Actually, we stick that MSR - EFER - into the trampoline header and then > each AP gets it written to in arch/x86/realmode/rm/trampoline_64.S > > But this is only from code staring - I'll confirm this tomorrow.
Ah, I had to stare it that for a bit to figure out how it works. setup_real_mode() reads MSR_EFER from the boot CPU and stores it in trampoline_header->efer. Then the other CPUs read that stored value in startup_32() and write it into their MSR.
> And if so, we should at least put comments in that trampoline code so > that people do not remove the MSR writes. > > Or, actually, we should simply write it again because it is the init > path and not really a hot path but it should damn well make sure that > that bit gets set.
Yeah, I think that would be good. Otherwise it's rather magical. That EFER MSR is a surprising place to put that bit.
-- Josh
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