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Subject[PATCH v2 0/6] clk: samsung: exynos850: Add missing clocks for PM
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As a part of preparation for PM enablement in Exynos850 clock driver,
this patch series implements CMU_G3D, and also main gate clocks for AUD
and HSI CMUs. The series brings corresponding changes to bindings, the
driver and SoC dts file.

Changes in v2:
- Rebased all patches on top of the most recent soc/for-next tree
- Added A-b and R-b tags
- Minor fixes

Sam Protsenko (6):
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
clk: samsung: clk-pll: Implement pll0818x PLL type
clk: samsung: exynos850: Implement CMU_G3D domain
clk: samsung: exynos850: Add AUD and HSI main gate clocks
arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC

.../clock/samsung,exynos850-clock.yaml | 19 +++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 ++
drivers/clk/samsung/clk-exynos850.c | 139 ++++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
include/dt-bindings/clock/exynos850.h | 28 +++-
6 files changed, 194 insertions(+), 3 deletions(-)

--
2.39.1

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