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SubjectRe: [PATCH 1/2] dt-bindings: phy: realtek: Add Realtek DHC RTD SoC PCIe PHY
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On 07/12/2023 11:10, TY_Chang[張子逸] wrote:
> Hi Krzysztof,
>
> Thank you for the review.
>
>> On 01/12/2023 11:52, Tzuyi Chang wrote:
>>> + "#phy-cells":
>>> + const: 0
>>> +
>>> + nvmem-cells:
>>> + maxItems: 1
>>> + description:
>>> + Phandle to nvmem cell that contains 'Tx swing trim'
>>> + tuning parameter value for PCIe phy.
>>> +
>>> + nvmem-cell-names:
>>> + items:
>>> + - const: tx_swing_trim
>>> +
>>> + realtek,pcie-syscon:
>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>> + description: phandle of syscon used to control PCIe MDIO register.
>>
>> Why this does not have reg property but syscon? This looks hacky.
>>
>
> Our PCIe PHY driver needs to access two registers:
> 1. PCIe MDIO register: Utilized for configuring the PCIe PHY.
> 2. PCIe MAC Link Control and Link Status Register: Use to get the current
> link speed for calibration purposes.
>
> Both these registers reside within the PCIe controller registers. The PCIe
> driver has mapped these register address region, so I use regmap to access
> these registers.

Hm, isn't in such case PCIe PHY a child of the PCIe controller? How is
it with resources, like power domains or regulators?

Best regards,
Krzysztof

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