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    Subject[PATCH v2 04/16] clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks
    Date
    Add missing QREF clocks for UFS MEM and UFS CARD controllers.

    Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++
    1 file changed, 28 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
    index ae2147381559..544567db45f1 100644
    --- a/drivers/clk/qcom/gcc-sc8180x.c
    +++ b/drivers/clk/qcom/gcc-sc8180x.c
    @@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
    },
    };

    +static struct clk_branch gcc_ufs_card_clkref_en = {
    + .halt_reg = 0x8c004,
    + .halt_check = BRANCH_HALT,
    + .clkr = {
    + .enable_reg = 0x8c004,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_ufs_card_clkref_en",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_branch gcc_ufs_card_ahb_clk = {
    .halt_reg = 0x75014,
    .halt_check = BRANCH_HALT,
    @@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
    },
    };

    +static struct clk_branch gcc_ufs_mem_clkref_en = {
    + .halt_reg = 0x8c000,
    + .halt_check = BRANCH_HALT,
    + .clkr = {
    + .enable_reg = 0x8c000,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_ufs_mem_clkref_en",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_branch gcc_ufs_phy_ahb_clk = {
    .halt_reg = 0x77014,
    .halt_check = BRANCH_HALT,
    @@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
    [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
    [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
    [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
    + [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr,
    [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
    [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
    [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
    @@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
    [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
    [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
    [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
    + [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr,
    [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
    [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
    [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
    --
    2.25.1

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