Messages in this thread |  | | Subject | Re: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property | | From | Stephen Boyd <> | | Date | Sun, 17 Dec 2023 22:32:30 -0800 |
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Quoting Alvin Šipraga (2023-11-24 05:17:43) > From: Alvin Šipraga <alsi@bang-olufsen.dk> > > For applications where the PLL must be adjusted without glitches in the > clock output(s), a new silabs,pll-reset-mode property is added. It > can be used to specify whether or not the PLL should be reset after > adjustment. Resetting is known to cause glitches. > > For compatibility with older device trees, it must be assumed that the > default PLL reset mode is to unconditionally reset after adjustment. > > Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> > Cc: Rabeeh Khoury <rabeeh@solid-run.com> > Cc: Jacob Siverskog <jacob@teenage.engineering> > Cc: Sergej Sawazki <sergej@taudac.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> > ---
Applied to clk-next
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