Messages in this thread | | | From | Namhyung Kim <> | Date | Mon, 11 Dec 2023 15:01:55 -0800 | Subject | Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors |
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On Mon, Dec 11, 2023 at 5:54 AM Ravi Bangoria <ravi.bangoria@amd.com> wrote: > > Hi Namhyung, > > >>>> By default, Perf uses precise cycles event when no explicit event is > >>>> specified by user. Precise cycles event is forwarded to ibs_op// pmu > >>>> on AMD. However, IBS has hw issue on certain Zen2 processors where > >>>> it might raise NMI without sample_valid bit set, which causes Unknown > >>>> NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter > >>>> Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So, > >>>> use non-precise cycles as default event on affected processors. > >>> > >>> It seems like a kernel issue, do we have a kernel patch not to forward > >>> precise cycles or instructions events to IBS on the affected CPUs? > >> > >> I'm not sure how it's a kernel issue. User can use ibs_op// pmu directly > >> and might hit the hw bug. > > > > Sorry for the late reply. I know it's the user's fault when using ibs_op// > > directly but I think the kernel should not forward cycles:pp to IBS. > > For all AMD zen uarchs, cycles:p is same as ibs_op// (man perf-list has > more detail). It's confusing if ibs_op// works but cycles:p fails on the > same machine.
Make sense. Probably perf tools can provide a more detailed message about the situation.
> > No strong opinion though. I can prepare a kernel patch, if you want.
I have a report that these unknown NMI messages caused some performance issues. So maybe we need to be safe by not using IBS automatically. I've also posted a patch to rate-limit the message itself.
Thanks, Namhyung
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