Messages in this thread | | | Date | Mon, 11 Dec 2023 17:46:19 +0100 | From | Andrea Parri <> | Subject | Re: [PATCH v2 3/4] membarrier: riscv: Provide core serializing command |
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> > /* > > * The membarrier system call requires a full memory barrier > > * after storing to rq->curr, before going back to user-space. > > + * > > + * The barrier is also needed for the SYNC_CORE command when > > + * switching between processes; in particular, on a transition > > + * from a thread belonging to another mm to a thread belonging > > + * to the mm for which a membarrier SYNC_CORE is done on CPU0: > > + * > > + * - [CPU0] sets all bits in the mm icache_stale_mask. > > + * > > + * - [CPU1] store to rq->curr (by the scheduler). > > + * > > + * - [CPU0] loads rq->curr within membarrier and observes > > + * cpu_rq(1)->curr->mm != mm, so the IPI is skipped on > > + * CPU1; this means membarrier relies on switch_mm() to > > + * issue the sync-core. > > + * > > + * - [CPU1] switch_mm() loads icache_stale_mask; if the bit > > + * is zero, switch_mm() may incorrectly skip the sync-core. > > + * > > + * Matches the full barrier in membarrier_private_expedited(). > > There are two full barriers in membarrier_private_expedited(). We > should clearly state which one it matches, and update the associated > barrier to state that it matches this barrier as well.
Agreed, will do.
Andrea
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