Messages in this thread Patch in this message | | | From | Michal Simek <> | Subject | [PATCH v3 2/2] dt-bindings: soc: Add new board description for MicroBlaze V | Date | Wed, 22 Nov 2023 11:23:13 +0100 |
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MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. Processor can be used with standard AMD/Xilinx IPs including interrupt controller and timer.
Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ---
Changes in v3: - Add Krzysztof's ACK
Changes in v2: - Put MicroBlaze V description to xilinx.yaml - Add qemu target platform as platform used for testing.
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index f57ed0347894..ec8155a343d0 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -132,6 +132,11 @@ properties: - const: xlnx,zynqmp-smk-k26 - const: xlnx,zynqmp + - description: AMD MicroBlaze V (QEMU) + items: + - const: qemu,mbv + - const: amd,mbv + additionalProperties: true ... -- 2.36.1
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