Messages in this thread | | | From | Fei Shao <> | Date | Thu, 23 Nov 2023 12:03:16 +0800 | Subject | Re: [PATCH v3 1/3] clk: mediatek: clk-mux: Support custom parent indices for muxes |
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On Fri, Nov 3, 2023 at 6:25 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Add support for customized parent indices for MediaTek muxes: this is > necessary for the case in which we want to exclude some clocks from > a mux's parent clocks list, where the exclusions are not from the > very bottom of the list but either in the middle or the beginning. > > Example: > - MUX1 (all parents) > - parent1; idx=0 > - parent2; idx=1 > - parent3; idx=2 > > - MUX1 (wanted parents) > - parent1; idx=0 > - parent3; idx=2 > > To achieve that add a `parent_index` array pointer to struct mtk_mux, > then in .set_parent(), .get_parent() callbacks check if this array > was populated and eventually get the index from that. > > Also, to avoid updating all clock drivers for all SoCs, rename the > "main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and > add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has > been reintroduced as being fully compatible with the older version. > > The new parent_index can be specified with the new `_INDEXED` > variants of the MUX_GATE_CLR_SET_UPD_xxxx macros. > > Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested on MT8188 with a Type-C -> DP adapter to an extended display Gigabyte M32U. The DP output reacts smoothly to resolution switch and refresh rate change, and the internal eDP output also never freezes.
Reviewed-by: Fei Shao <fshao@chromium.org> Tested-by: Fei Shao <fshao@chromium.org>
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