Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 21 Nov 2023 15:55:13 +0100 | From | Johan Hovold <> | Subject | Re: [PATCH v4 3/3] arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent |
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On Tue, Nov 21, 2023 at 08:08:13PM +0530, Mrinmay Sarkar wrote: > The PCIe EP controller on SA8775P supports cache coherency, hence add > the "dma-coherent" property to mark it as such. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 7eab458..ab01efe 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3620,6 +3620,7 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; > interconnect-names = "pcie-mem", "cpu-pcie"; > > + dma-coherent; > iommus = <&pcie_smmu 0x0000 0x7f>; > resets = <&gcc GCC_PCIE_0_BCR>; > reset-names = "core";
What tree is this against?
Both controllers are already marked as dma-coherent in mainline so this patch makes no sense (and the context also looks wrong).
It was even you added them apparently:
489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
Johan
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