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    Subject[PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
    There are few places where clk_init_data structure doesn't carry the const
    qualifier. Let's add the same.

    Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
    ---
    Changes in V2:
    - New patch
    ---
    drivers/clk/qcom/gcc-ipq5332.c | 38 +++++++++++++++++++-------------------
    1 file changed, 19 insertions(+), 19 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
    index f98591148a97..66d5399798fe 100644
    --- a/drivers/clk/qcom/gcc-ipq5332.c
    +++ b/drivers/clk/qcom/gcc-ipq5332.c
    @@ -65,7 +65,7 @@ static struct clk_alpha_pll gpll0_main = {
    static struct clk_fixed_factor gpll0_div2 = {
    .mult = 1,
    .div = 2,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gpll0_div2",
    .parent_hws = (const struct clk_hw *[]) {
    &gpll0_main.clkr.hw },
    @@ -78,7 +78,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
    .offset = 0x20000,
    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
    .width = 4,
    - .clkr.hw.init = &(struct clk_init_data) {
    + .clkr.hw.init = &(const struct clk_init_data) {
    .name = "gpll0",
    .parent_hws = (const struct clk_hw *[]) {
    &gpll0_main.clkr.hw },
    @@ -106,7 +106,7 @@ static struct clk_alpha_pll_postdiv gpll2 = {
    .offset = 0x21000,
    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
    .width = 4,
    - .clkr.hw.init = &(struct clk_init_data) {
    + .clkr.hw.init = &(const struct clk_init_data) {
    .name = "gpll2_main",
    .parent_hws = (const struct clk_hw *[]) {
    &gpll2_main.clkr.hw },
    @@ -145,7 +145,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
    .offset = 0x22000,
    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
    .width = 4,
    - .clkr.hw.init = &(struct clk_init_data) {
    + .clkr.hw.init = &(const struct clk_init_data) {
    .name = "gpll4",
    .parent_hws = (const struct clk_hw *[]) {
    &gpll4_main.clkr.hw },
    @@ -572,7 +572,7 @@ static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
    .clkr = {
    .enable_reg = 0x2907c,
    .enable_mask = BIT(1),
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x1_0_rchg_clk",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
    @@ -615,7 +615,7 @@ static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
    .clkr = {
    .enable_reg = 0x2a078,
    .enable_mask = BIT(1),
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x1_1_rchg_clk",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
    @@ -678,7 +678,7 @@ static struct clk_branch gcc_pcie3x2_rchg_clk = {
    .clkr = {
    .enable_reg = 0x28078,
    .enable_mask = BIT(1),
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x2_rchg_clk",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_pcie3x2_rchg_clk_src.clkr.hw },
    @@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
    static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
    .reg = 0x28064,
    .clkr = {
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x2_pipe_clk_src",
    .parent_data = &(const struct clk_parent_data) {
    .index = DT_PCIE_2LANE_PHY_PIPE_CLK,
    @@ -725,7 +725,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
    static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
    .reg = 0x29064,
    .clkr = {
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x1_0_pipe_clk_src",
    .parent_data = &(const struct clk_parent_data) {
    .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
    @@ -739,7 +739,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
    static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
    .reg = 0x2a064,
    .clkr = {
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_pcie3x1_1_pipe_clk_src",
    .parent_data = &(const struct clk_parent_data) {
    .index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
    @@ -826,7 +826,7 @@ static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
    static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
    .mult = 1,
    .div = 2,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_qdss_tsctr_div2_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_tsctr_clk_src.clkr.hw },
    @@ -839,7 +839,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
    static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
    .mult = 1,
    .div = 3,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_qdss_tsctr_div3_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_tsctr_clk_src.clkr.hw },
    @@ -851,7 +851,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
    static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
    .mult = 1,
    .div = 4,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_qdss_tsctr_div4_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_tsctr_clk_src.clkr.hw },
    @@ -863,7 +863,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
    static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
    .mult = 1,
    .div = 8,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_qdss_tsctr_div8_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_tsctr_clk_src.clkr.hw },
    @@ -875,7 +875,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
    static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
    .mult = 1,
    .div = 16,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_qdss_tsctr_div16_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_tsctr_clk_src.clkr.hw },
    @@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
    static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
    .mult = 1,
    .div = 2,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_system_noc_bfdcd_div2_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_system_noc_bfdcd_clk_src.clkr.hw },
    @@ -1069,7 +1069,7 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
    static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
    .reg = 0x2c074,
    .clkr = {
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_usb0_pipe_clk_src",
    .parent_data = &(const struct clk_parent_data) {
    .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
    @@ -1111,7 +1111,7 @@ static struct clk_rcg2 gcc_xo_clk_src = {
    static struct clk_fixed_factor gcc_xo_div4_clk_src = {
    .mult = 1,
    .div = 4,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_xo_div4_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_xo_clk_src.clkr.hw },
    @@ -2431,7 +2431,7 @@ static struct clk_branch gcc_qdss_etr_usb_clk = {
    static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
    .mult = 1,
    .div = 6,
    - .hw.init = &(struct clk_init_data) {
    + .hw.init = &(const struct clk_init_data) {
    .name = "gcc_eud_at_div_clk_src",
    .parent_hws = (const struct clk_hw *[]) {
    &gcc_qdss_at_clk_src.clkr.hw },
    --
    2.34.1

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