Messages in this thread | | | Date | Mon, 20 Nov 2023 08:49:16 +0200 | Subject | Re: [PATCH v1 1/1] mmc: sdhci-of-dwcmshc: Enable timeout quirk for BlueField-3 SoC | From | Adrian Hunter <> |
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On 18/11/23 15:46, Liming Sun wrote: > This commit enables SDHCI_QUIRK_BROKEN_TIMEOUT_VAL to solve the > intermittent eMMC timeout issue reported on some cards under eMMC > stress test. > > Reported error message: > dwcmshc MLNXBF30:00: __mmc_blk_ioctl_cmd: data error -110
Were you able to determine the root cause? For example, is the host controller timeout correct, is the eMMC providing correct timeout values, is the mmc subsystem calculating a correct value, is sdhci programming a correct value?
If there are problems outside the host controller then we need to address them also.
> > Signed-off-by: Liming Sun <limings@nvidia.com>
Fixes tag?
> --- > drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c > index 3a3bae6948a8..3c8fe8aec558 100644 > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > @@ -365,7 +365,8 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { > #ifdef CONFIG_ACPI > static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { > .ops = &sdhci_dwcmshc_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | > + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, > .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > SDHCI_QUIRK2_ACMD23_BROKEN, > };
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