Messages in this thread | ![/](/images/icornerl.gif) | | Subject | Re: [PATCH 03/13] net: ravb: Make write access to CXR35 first before accessing other EMAC registers | From | Sergey Shtylyov <> | Date | Mon, 20 Nov 2023 22:44:46 +0300 |
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On 11/20/23 11:45 AM, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Hardware manual of RZ/G3S (and RZ/G2L) specifies the following on the > description of CXR35 register (chapter "PHY interface select register > (CXR35)"): "After release reset, make write-access to this register before > making write-access to other registers (except MDIOMOD). Even if not need > to change the value of this register, make write-access to this register > at least one time. Because RGMII/MII MODE is recognized by accessing this > register". > > The setup procedure for EMAC module (chapter "Setup procedure" of RZ/G3S, > RZ/G2L manuals) specifies the E-MAC.CXR35 register is the first EMAC > register that is to be configured. > > Note [A] from chapter "PHY interface select register (CXR35)" specifies > the following: > [A] The case which CXR35 SEL_XMII is used for the selection of RGMII/MII > in APB Clock 100 MHz. > (1) To use RGMII interface, Set ‘H’03E8_0000’ to this register. > (2) To use MII interface, Set ‘H’03E8_0002’ to this register. > > Take into account these indication. > > Fixes: 1089877ada8d ("ravb: Add RZ/G2L MII interface support")
The bug fixes should be submitted separately and against the net.git repo...
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
[...]
MBR, Sergey
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