Messages in this thread | | | From | Linus Walleij <> | Date | Tue, 14 Nov 2023 08:45:56 +0100 | Subject | Re: [PATCH v2 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register |
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On Fri, Oct 13, 2023 at 4:59 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> Existing Qualcomm SoCs have the LPASS pin controller slew rate control > in separate register, however this will change with upcoming Qualcomm > SoCs. The slew rate will be part of the main register for pin > configuration, thus second device IO address space is not needed. > > Prepare for supporting new SoCs by adding flag customizing the driver > behavior for slew rate. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patches applied.
Yours, Linus Walleij
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