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SubjectRe: [PATCH v2 1/2] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 binding
On Tue, Jan 03, 2023 at 08:34:18PM +0530, Bhupesh Sharma wrote:
> Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC.
>
> On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg'
> needs to be set first to 'enable' the eud module.
>
> So, update the dt-bindings to accommodate the third register
> property required by the driver on these SoCs.
>
> Cc: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
> index c98aab209bc5d..1dffe14868735 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
> @@ -18,12 +18,22 @@ properties:
> items:
> - enum:
> - qcom,sc7280-eud
> + - qcom,sm6115-eud
> - const: qcom,eud
>
> reg:
> + minItems: 2
> items:
> - description: EUD Base Register Region
> - description: EUD Mode Manager Register
> + - description: TCSR Check Register

So this is going to be a 4 byte region in the middle of the &tcsr block?

Could we instead make that a reference to &tcsr + offset?

Regards,
Bjorn

> +
> + reg-names:
> + minItems: 2
> + items:
> + - const: eud-base
> + - const: eud-mode-mgr
> + - const: tcsr-check-base
>
> interrupts:
> description: EUD interrupt
> --
> 2.38.1
>

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