Messages in this thread | | | Date | Tue, 3 Jan 2023 11:52:12 +0000 | Subject | Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2 | From | John Garry <> |
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On 03/01/2023 11:39, Jing Zhang wrote: > The formula of topdown L1 on neoverse-n2 is from ARM sbsa7.0 platform > design document [0], D37-38.
I think that I mentioned this before - if the these metrics are coming from an sbsa doc, then they are standard. As such, we can make them "arch std events" and put them in a common json such as sbsa.json, so that other cores may reuse.
You don't strictly have to do do this now, but it would be better.
Thanks, John
> > However, due to the wrong count of stall_slot and stall_slot_frontend on > neoverse-n2, the real stall_slot and real stall_slot_frontend need to > subtract cpu_cycles, so correct the expression of topdown metrics. > Reference from ARM neoverse-n2 errata notice [1], D117. > > Since neoverse-n2 does not yet support topdown L2, metricgroups such as > Cache, TLB, Branch, InstructionsMix, and PEutilization will be added to > further analysis of performance bottlenecks in the following patches. > Reference from ARM PMU guide [2][3].
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