Messages in this thread | | | Date | Tue, 24 Jan 2023 17:39:53 +0100 | Subject | Re: Internal vs. external barriers (was: Re: Interesting LKMM litmus test) | From | Jonas Oberhauser <> |
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On 1/24/2023 5:22 PM, Paul E. McKenney wrote: > I clearly recall some > store-based lack of ordering after a grace period from some years back, > and am thus far failing to reproduce it. > > And here is another attempt that herd7 actually does allow. > > So what did I mess up this time? ;-) > > Thanx, Paul > > ------------------------------------------------------------------------ > > C C-srcu-observed-4 > > (* > * Result: Sometimes > * > * The Linux-kernel implementation is suspected to forbid this. > *) > > {} > > P0(int *x, int *y, int *z, struct srcu_struct *s) > { > int r1; > > r1 = srcu_read_lock(s); > WRITE_ONCE(*y, 2); > WRITE_ONCE(*x, 1); > srcu_read_unlock(s, r1); > } > > P1(int *x, int *y, int *z, struct srcu_struct *s) > { > int r1; > > WRITE_ONCE(*y, 1); > synchronize_srcu(s); > WRITE_ONCE(*z, 2); > } > > P2(int *x, int *y, int *z, struct srcu_struct *s) > { > WRITE_ONCE(*z, 1); > smp_store_release(x, 2); > } > > exists (x=1 /\ y=1 /\ z=1)
I think even if you implement the unlock as mb() followed by some store that is read by the gp between mb()s, this would still be allowed.
I have already forgotten the specifics, but I think the power model allows certain stores never propagating somewhere? If z=2,z=1,x=2 never propagate to P0, you might start by executing P0, then P1, and then P2 at which point the memory system decides that x=1 overwrites x=2, and the latter simply doesn't propagate anywhere.
(I'll let anyone who has the model at hand correct me on this, because I have to take a walk now).
Have fun, jonas
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