Messages in this thread | | | Date | Mon, 23 Jan 2023 11:53:19 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH v3] riscv: Allow to downgrade paging mode from the command |
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Hey Alex,
On Mon, Jan 23, 2023 at 11:48:41AM +0100, Alexandre Ghiti wrote: > Add 2 early command line parameters that allow to downgrade satp mode > (using the same naming as x86): > - "no5lvl": use a 4-level page table (down from sv57 to sv48) > - "no4lvl": use a 3-level page table (down from sv57/sv48 to sv39) > > Note that going through the device tree to get the kernel command line > works with ACPI too since the efi stub creates a device tree anyway with > the command line. > > Also, as those params are treated very early in the boot process and we > use standard device tree functions that may be kasan instrumented, we > only enable them for !KASAN configurations. > > Reviewed-by: Björn Töpel <bjorn@kernel.org> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > ---
A changelog would be nice here, especially since this is a resend.
> .../admin-guide/kernel-parameters.txt | 9 ++- > arch/riscv/mm/init.c | 72 +++++++++++++++++-- > 2 files changed, 74 insertions(+), 7 deletions(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 6cfa6e3996cf..fd647412ec91 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -3578,8 +3578,15 @@ > emulation library even if a 387 maths coprocessor > is present. > > - no5lvl [X86-64] Disable 5-level paging mode. Forces > + no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces > + kernel to use 3-level paging instead. > + Note: On RISC-V, this can't be used when KASAN is > + enabled. > + > + no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces > kernel to use 4-level paging instead. > + Note: On RISC-V, this can't be used when KASAN is > + enabled. > > nofsgsbase [X86] Disables FSGSBASE instructions. >
For the improved descriptions & commit message: Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks, Conor.
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