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    Subject[RFC PATCH 23/23] x86/process: Reset hardware history in context switch
    Date
    Reset the classification history of the current task when switching to
    the next task. Hardware will start anew the classification of the next
    running task.

    Cc: Ben Segall <bsegall@google.com>
    Cc: Daniel Bristot de Oliveira <bristot@redhat.com>
    Cc: Dietmar Eggemann <dietmar.eggemann@arm.com>
    Cc: Len Brown <len.brown@intel.com>
    Cc: Mel Gorman <mgorman@suse.de>
    Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
    Cc: Steven Rostedt <rostedt@goodmis.org>
    Cc: Tim C. Chen <tim.c.chen@intel.com>
    Cc: Valentin Schneider <vschneid@redhat.com>
    Cc: x86@kernel.org
    Cc: linux-kernel@vger.kernel.org
    Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
    ---
    arch/x86/include/asm/hreset.h | 30 ++++++++++++++++++++++++++++++
    arch/x86/kernel/cpu/common.c | 10 ++++++++++
    arch/x86/kernel/process_32.c | 3 +++
    arch/x86/kernel/process_64.c | 3 +++
    4 files changed, 46 insertions(+)
    create mode 100644 arch/x86/include/asm/hreset.h

    diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h
    new file mode 100644
    index 000000000000..d68ca2fb8642
    --- /dev/null
    +++ b/arch/x86/include/asm/hreset.h
    @@ -0,0 +1,30 @@
    +/* SPDX-License-Identifier: GPL-2.0 */
    +#ifndef _ASM_X86_HRESET_H
    +
    +/**
    + * HRESET - History reset. Available since binutils v2.36.
    + *
    + * Request the processor to reset the history of task classification on the
    + * current logical processor. The history components to be
    + * reset are specified in %eax. Only bits specified in CPUID(0x20).EBX
    + * and enabled in the IA32_HRESET_ENABLE MSR can be selected.
    + *
    + * The assembly code looks like:
    + *
    + * hreset %eax
    + *
    + * The corresponding machine code looks like:
    + *
    + * F3 0F 3A F0 ModRM Imm
    + *
    + * The value of ModRM is 0xc0 to specify %eax register addressing.
    + * The ignored immediate operand is set to 0.
    + *
    + * The instruction is documented in the Intel SDM.
    + */
    +
    +#define __ASM_HRESET ".byte 0xf3, 0xf, 0x3a, 0xf0, 0xc0, 0x0"
    +
    +void reset_hardware_history(void);
    +
    +#endif /* _ASM_X86_HRESET_H */
    diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
    index 108642fe6761..4622a0ebf8a1 100644
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -52,6 +52,7 @@
    #include <asm/cpu.h>
    #include <asm/mce.h>
    #include <asm/msr.h>
    +#include <asm/hreset.h>
    #include <asm/memtype.h>
    #include <asm/microcode.h>
    #include <asm/microcode_intel.h>
    @@ -413,6 +414,15 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c)

    static u32 hardware_history_features __read_mostly;

    +void reset_hardware_history(void)
    +{
    + if (!static_cpu_has(X86_FEATURE_HRESET))
    + return;
    +
    + asm volatile("mov %0, %%eax;" __ASM_HRESET "\n" : :
    + "r" (hardware_history_features) : "%rax");
    +}
    +
    static __always_inline void setup_hreset(struct cpuinfo_x86 *c)
    {
    if (!cpu_feature_enabled(X86_FEATURE_HRESET))
    diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
    index 2f314b170c9f..74d8ad83e0b3 100644
    --- a/arch/x86/kernel/process_32.c
    +++ b/arch/x86/kernel/process_32.c
    @@ -52,6 +52,7 @@
    #include <asm/switch_to.h>
    #include <asm/vm86.h>
    #include <asm/resctrl.h>
    +#include <asm/hreset.h>
    #include <asm/proto.h>

    #include "process.h"
    @@ -214,6 +215,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
    /* Load the Intel cache allocation PQR MSR. */
    resctrl_sched_in();

    + reset_hardware_history();
    +
    return prev_p;
    }

    diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
    index 1962008fe743..0b175f30f359 100644
    --- a/arch/x86/kernel/process_64.c
    +++ b/arch/x86/kernel/process_64.c
    @@ -53,6 +53,7 @@
    #include <asm/xen/hypervisor.h>
    #include <asm/vdso.h>
    #include <asm/resctrl.h>
    +#include <asm/hreset.h>
    #include <asm/unistd.h>
    #include <asm/fsgsbase.h>
    #ifdef CONFIG_IA32_EMULATION
    @@ -657,6 +658,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
    /* Load the Intel cache allocation PQR MSR. */
    resctrl_sched_in();

    + reset_hardware_history();
    +
    return prev_p;
    }

    --
    2.25.1
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