Messages in this thread | | | From | Rahul Tanwar <> | Subject | Re: [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO | Date | Thu, 29 Sep 2022 05:29:57 +0000 |
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Hi Stephen,
Thanks for review and response.
On 29/9/2022 8:14 am, Stephen Boyd wrote: > This email was sent from outside of MaxLinear. > > > Quoting Rahul Tanwar (2022-09-21 23:24:24) >> diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c >> index 3179557b5f78..c83083affe88 100644 >> --- a/drivers/clk/x86/clk-cgu-pll.c >> +++ b/drivers/clk/x86/clk-cgu-pll.c >> @@ -1,8 +1,9 @@ >> // SPDX-License-Identifier: GPL-2.0 >> /* >> + * Copyright (C) 2020-2022 MaxLinear, Inc. >> * Copyright (C) 2020 Intel Corporation. >> - * Zhu YiXin <yixin.zhu@intel.com> >> - * Rahul Tanwar <rahul.tanwar@intel.com> >> + * Zhu Yixin <yzhu@maxlinear.com> > > Does Zhu Yixin approve? They're not Cced on this patch.
Zhu Yixin is part of linux-lgm-soc@maxlinear.com mail list which is CCed here. In v3, i will separately CC Yixin and request him to review again and provide a Reviewed-by tag if no concerns.
Thanks, Rahul
> >> + * Rahul Tanwar <rtanwar@maxlinear.com> >> */ >> >> #include <linux/clk-provider.h> > >
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