Messages in this thread | | | Date | Wed, 21 Sep 2022 12:10:08 +0200 | Subject | Re: Similar SoCs with different CPUs and interrupt bindings | From | Krzysztof Kozlowski <> |
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On 21/09/2022 12:08, Geert Uytterhoeven wrote: >> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> index ff6aab388eb7..0ecca775fa3f 100644 >> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> @@ -8,6 +8,8 @@ >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/clock/r9a07g043-cpg.h> >> >> +#define SOC_PERIPHERAL_IRQ_NUMBER(na) (na + 32) >> +#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr SOC_PERIPHERAL_IRQ_NUMBER(na) > > #define SOC_PERIPHERAL_IRQ(nr, flags) GIC_SPI > SOC_PERIPHERAL_IRQ_NUMBER(nr) flags
Right. Let's consider my code just proof-of-concept :)
Best regards, Krzysztof
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