| From | Rob Herring <> | Date | Tue, 30 Aug 2022 07:47:53 -0500 | Subject | Re: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache |
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On Tue, Aug 30, 2022 at 3:36 AM Ben Dooks <ben.dooks@sifive.com> wrote: > > With newer cores such as the p550, the SiFive composable cache can be > a level 3 cache. Update the cache level to be one of 2 or 3. > > Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > --- > Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Please send DT patches to the DT list. Resend so checks run.
Rob
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