Messages in this thread | | | Date | Wed, 24 Aug 2022 16:27:14 +0300 | Subject | Re: [PATCH v3 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks | From | Krzysztof Kozlowski <> |
| |
On 24/08/2022 12:33, Conor Dooley wrote: > On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the > ordinal corners of the chip, which our documentation refers to as > "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are > highly configurable & many of the input clocks are optional. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards, Krzysztof
| |