Messages in this thread Patch in this message | | | Date | Mon, 22 Aug 2022 16:39:32 +0200 | From | Peter Zijlstra <> | Subject | Re: [RESEND PATCH] perf/x86/intel: Fix unchecked MSR access error for Alder Lake N |
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On Mon, Aug 22, 2022 at 09:28:31AM -0400, Liang, Kan wrote: > > > On 2022-08-19 10:38 a.m., Peter Zijlstra wrote: > > On Thu, Aug 18, 2022 at 11:15:30AM -0700, kan.liang@linux.intel.com wrote: > >> From: Kan Liang <kan.liang@linux.intel.com> > >> > >> For some Alder Lake N machine, the below unchecked MSR access error may be > >> triggered. > >> > >> [ 0.088017] rcu: Hierarchical SRCU implementation. > >> [ 0.088017] unchecked MSR access error: WRMSR to 0x38f (tried to write > >> 0x0001000f0000003f) at rIP: 0xffffffffb5684de8 (native_write_msr+0x8/0x30) > >> [ 0.088017] Call Trace: > >> [ 0.088017] <TASK> > >> [ 0.088017] __intel_pmu_enable_all.constprop.46+0x4a/0xa0 > > > > FWIW, I seem to get the same error when booting KVM on my ADL. I'm > > fairly sure the whole CPUID vs vCPU thing is a trainwreck. > > We will enhance the CPUID to address the issues. Hopefully, we can have > them supported in the next generation. >
How about this?
--- [ 0.170231] Performance Events: Alderlake Hybrid events, full-width counters, Intel PMU driver. [ 0.171420] core: hybrid PMU and virt are incompatible
arch/x86/events/intel/core.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 2db93498ff71..232e24324fd7 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4473,6 +4473,11 @@ static bool init_hybrid_pmu(int cpu) struct x86_hybrid_pmu *pmu = NULL; int i; + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { + pr_warn_once("hybrid PMU and virt are incompatible\n"); + return false; + } + if (!cpu_type && x86_pmu.get_hybrid_cpu_type) cpu_type = x86_pmu.get_hybrid_cpu_type();
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