Messages in this thread | | | From | Doug Anderson <> | Date | Wed, 17 Aug 2022 15:54:35 -0700 | Subject | Re: [PATCH] drm/bridge: ps8640: Add double reset T4 and T5 to power-on sequence |
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Hi,
On Mon, Aug 15, 2022 at 2:39 AM Hsin-Yi Wang <hsinyi@chromium.org> wrote: > > The double reset power-on sequence is a workaround for the hardware > flaw in some chip that SPI Clock output glitch and cause internal MPU > unable to read firmware correctly. The sequence is suggested in ps8640 > application note. > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/bridge/parade-ps8640.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c > index 49107a6cdac18..d7483c13c569b 100644 > --- a/drivers/gpu/drm/bridge/parade-ps8640.c > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c > @@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct device *dev) > gpiod_set_value(ps_bridge->gpio_reset, 1); > usleep_range(2000, 2500); > gpiod_set_value(ps_bridge->gpio_reset, 0); > + /* Double reset for T4 and T5 */ > + msleep(50); > + gpiod_set_value(ps_bridge->gpio_reset, 1); > + msleep(50); > + gpiod_set_value(ps_bridge->gpio_reset, 0);
We really need another 100 ms here? ps8640 is already quite slow at powering itself up and that has a real user impact. Why was it only 2.5 ms for the first reset and 50 ms for the second?
-Doug
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