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    Subject[PATCH 5.19 0696/1157] iio: frequency: adf4371: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 0bb5675befe666eeed71ad808426cf2ec1c9a714 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: 7f699bd14913 ("iio: frequency: adf4371: Add support for ADF4371 PLL")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-68-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/frequency/adf4371.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
    index ecd5e18995ad..135c8cedc33d 100644
    --- a/drivers/iio/frequency/adf4371.c
    +++ b/drivers/iio/frequency/adf4371.c
    @@ -175,7 +175,7 @@ struct adf4371_state {
    unsigned int mod2;
    unsigned int rf_div_sel;
    unsigned int ref_div_factor;
    - u8 buf[10] ____cacheline_aligned;
    + u8 buf[10] __aligned(IIO_DMA_MINALIGN);
    };

    static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
    --
    2.35.1


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