lkml.org 
[lkml]   [2022]   [Aug]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.19 0421/1157] drm/vc4: hdmi: Fix timings for interlaced modes
    Date
    From: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>

    [ Upstream commit 0ee5a40152b15f200ed3a0d51e8aa782ea979c6a ]

    Increase the number of post-sync blanking lines on odd fields instead of
    decreasing it on even fields. This makes the total number of lines
    properly match the modelines.

    Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
    pixels_per_clock into account, causing some displays to invert the
    fields when driven by bcm2711.

    Fixes: 682e62c45406 ("drm/vc4: Fix support for interlaced modes on HDMI.")
    Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
    Link: https://lore.kernel.org/r/20220613144800.326124-31-maxime@cerno.tech
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/vc4/vc4_crtc.c | 7 ++++---
    drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------
    2 files changed, 10 insertions(+), 9 deletions(-)

    diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
    index 12a5944ee980..b2628afcb327 100644
    --- a/drivers/gpu/drm/vc4/vc4_crtc.c
    +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
    @@ -346,7 +346,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
    PV_HORZB_HACTIVE));

    CRTC_WRITE(PV_VERTA,
    - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
    + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
    + interlace,
    PV_VERTA_VBP) |
    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
    PV_VERTA_VSYNC));
    @@ -358,7 +359,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
    if (interlace) {
    CRTC_WRITE(PV_VERTA_EVEN,
    VC4_SET_FIELD(mode->crtc_vtotal -
    - mode->crtc_vsync_end - 1,
    + mode->crtc_vsync_end,
    PV_VERTA_VBP) |
    VC4_SET_FIELD(mode->crtc_vsync_end -
    mode->crtc_vsync_start,
    @@ -378,7 +379,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
    PV_VCONTROL_CONTINUOUS |
    (is_dsi ? PV_VCONTROL_DSI : 0) |
    PV_VCONTROL_INTERLACE |
    - VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
    + VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
    PV_VCONTROL_ODD_DELAY));
    CRTC_WRITE(PV_VSYNCD_EVEN, 0);
    } else {
    diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
    index f3e0de6515e0..674bd29a7cf2 100644
    --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
    +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
    @@ -988,12 +988,12 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
    VC4_HDMI_VERTA_VFP) |
    VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
    u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
    - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
    + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
    + interlaced,
    VC4_HDMI_VERTB_VBP));
    u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
    VC4_SET_FIELD(mode->crtc_vtotal -
    - mode->crtc_vsync_end -
    - interlaced,
    + mode->crtc_vsync_end,
    VC4_HDMI_VERTB_VBP));
    unsigned long flags;

    @@ -1041,12 +1041,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
    VC5_HDMI_VERTA_VFP) |
    VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
    u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
    - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
    + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
    + interlaced,
    VC4_HDMI_VERTB_VBP));
    u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
    VC4_SET_FIELD(mode->crtc_vtotal -
    - mode->crtc_vsync_end -
    - interlaced,
    + mode->crtc_vsync_end,
    VC4_HDMI_VERTB_VBP));
    unsigned long flags;
    unsigned char gcp;
    --
    2.35.1


    \
     
     \ /
      Last update: 2022-09-17 16:26    [W:3.560 / U:0.092 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site