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    Subject[PATCH 5.19 0303/1157] pwm: lpc18xx: Fix period handling
    Date
    From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

    [ Upstream commit 8933d30c5f468d6cc1e4bf9bb535149da35f202e ]

    The calculation:

    val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX;
    do_div(val, lpc18xx_pwm->clk_rate);
    lpc18xx_pwm->max_period_ns = val;

    is bogus because with NSEC_PER_SEC = 1000000000,
    LPC18XX_PWM_TIMER_MAX = 0xffffffff and clk_rate < NSEC_PER_SEC this
    overflows the (on lpc18xx (i.e. ARM32) 32 bit wide) unsigned int
    .max_period_ns. This results (dependant of the actual clk rate) in an
    arbitrary limitation of the maximal period. E.g. for clkrate =
    333333333 (Hz) we get max_period_ns = 9 instead of 12884901897.

    So make .max_period_ns an u64 and pass period and duty as u64 to not
    discard relevant digits. And also make use of mul_u64_u64_div_u64()
    which prevents all overflows assuming clk_rate < NSEC_PER_SEC.

    Fixes: 841e6f90bb78 ("pwm: NXP LPC18xx PWM/SCT driver")
    Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
    Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pwm/pwm-lpc18xx-sct.c | 55 +++++++++++++++++++++++++----------
    1 file changed, 39 insertions(+), 16 deletions(-)

    diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c
    index 272e0b5d01b8..0de575747782 100644
    --- a/drivers/pwm/pwm-lpc18xx-sct.c
    +++ b/drivers/pwm/pwm-lpc18xx-sct.c
    @@ -98,7 +98,7 @@ struct lpc18xx_pwm_chip {
    unsigned long clk_rate;
    unsigned int period_ns;
    unsigned int min_period_ns;
    - unsigned int max_period_ns;
    + u64 max_period_ns;
    unsigned int period_event;
    unsigned long event_map;
    struct mutex res_lock;
    @@ -145,40 +145,48 @@ static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
    mutex_unlock(&lpc18xx_pwm->res_lock);
    }

    -static void lpc18xx_pwm_config_period(struct pwm_chip *chip, int period_ns)
    +static void lpc18xx_pwm_config_period(struct pwm_chip *chip, u64 period_ns)
    {
    struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
    - u64 val;
    + u32 val;

    - val = (u64)period_ns * lpc18xx_pwm->clk_rate;
    - do_div(val, NSEC_PER_SEC);
    + /*
    + * With clk_rate < NSEC_PER_SEC this cannot overflow.
    + * With period_ns < max_period_ns this also fits into an u32.
    + * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
    + * we have val >= 1.
    + */
    + val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);

    lpc18xx_pwm_writel(lpc18xx_pwm,
    LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
    - (u32)val - 1);
    + val - 1);

    lpc18xx_pwm_writel(lpc18xx_pwm,
    LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
    - (u32)val - 1);
    + val - 1);
    }

    static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
    - struct pwm_device *pwm, int duty_ns)
    + struct pwm_device *pwm, u64 duty_ns)
    {
    struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
    struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
    - u64 val;
    + u32 val;

    - val = (u64)duty_ns * lpc18xx_pwm->clk_rate;
    - do_div(val, NSEC_PER_SEC);
    + /*
    + * With clk_rate < NSEC_PER_SEC this cannot overflow.
    + * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
    + */
    + val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);

    lpc18xx_pwm_writel(lpc18xx_pwm,
    LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
    - (u32)val);
    + val);

    lpc18xx_pwm_writel(lpc18xx_pwm,
    LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event),
    - (u32)val);
    + val);
    }

    static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
    @@ -377,12 +385,27 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev)
    goto disable_pwmclk;
    }

    + /*
    + * If clkrate is too fast, the calculations in .apply() might overflow.
    + */
    + if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) {
    + ret = dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
    + goto disable_pwmclk;
    + }
    +
    + /*
    + * If clkrate is too fast, the calculations in .apply() might overflow.
    + */
    + if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) {
    + ret = dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
    + goto disable_pwmclk;
    + }
    +
    mutex_init(&lpc18xx_pwm->res_lock);
    mutex_init(&lpc18xx_pwm->period_lock);

    - val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX;
    - do_div(val, lpc18xx_pwm->clk_rate);
    - lpc18xx_pwm->max_period_ns = val;
    + lpc18xx_pwm->max_period_ns =
    + mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);

    lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
    lpc18xx_pwm->clk_rate);
    --
    2.35.1


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