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    Subject[PATCH 5.19 0676/1157] iio: dac: ad5504: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 00b9737caa5aaed5cf45a7c7498edf5957efa3b2 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: 0dbe59c7a788 ("iio:ad5504: Do not store transfer buffers on the stack")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Cc: Lars-Peter Clausen <lars@metafoo.de>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-48-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/dac/ad5504.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/dac/ad5504.c b/drivers/iio/dac/ad5504.c
    index a0817e799cc0..e6c5be728bb2 100644
    --- a/drivers/iio/dac/ad5504.c
    +++ b/drivers/iio/dac/ad5504.c
    @@ -54,7 +54,7 @@ struct ad5504_state {
    unsigned pwr_down_mask;
    unsigned pwr_down_mode;

    - __be16 data[2] ____cacheline_aligned;
    + __be16 data[2] __aligned(IIO_DMA_MINALIGN);
    };

    /*
    --
    2.35.1


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